Modern electronic devices require various types of amplifies for any number of applications, including low noise amplifiers and power amplifiers. Cascode amplifier circuits, in particular, are often incorporated into amplifier designs. For example, cascode amplifier circuits may be used in very high frequency amplifiers that work at millimeter wave frequencies (e.g., above 20 GHz). Examples of electronic devices that typically incorporate amplifiers having cascode amplifier circuits include Global Positioning System (GPS) transceivers, cellular telephones, cellular base station amplifiers, personal digital assistants (PDAs) and electronic organizers, portable electronic games, and the like, although such circuits may be included in nearly all types of electronic devices.
FIG. 1 is a circuit diagram depicting a conventional amplifier circuit 100, which includes cascode amplifier 110 and biasing circuit 140 for biasing the cascode amplifier 110. The cascode amplifier 110 includes cascode transistors 111 and 112 connected at low impedance node N101. Transistor 111 has a source connected to a low voltage supply (e.g., ground), a drain connected to node N101, and a gate connected to input node Nin. The gate of transistor 111 is also connected to a gate of transistor 123 in biasing circuit 140 through resistor R103, thus forming a current mirror 120. Transistor 112 has a source connected node N101, a drain connected to output node Nout and a gate connected to low impedance node N102 in biasing circuit 140 through resistor R104. Output node Nout is connected to a power supply voltage source, which provides power supply voltage Vdd via inductor L116.
Generally, radio frequency (RF) signals are received at input port RFin, and pass though input capacitor Cin to input node Nin. Corresponding amplified RF signals are output from output node Nout, passing through output capacitor Cout to output port RFout.
Referring to FIG. 1, transistors 111 and 112 share the same current IDD, provided through by inductor L116, which receives power supply voltage Vdd. The gate of transistor 112 is biased from a voltage source with minimal source impedance. Linearity may be improved by the first gain device, i.e., transistor 111, operating with no drain voltage swing, since it is connected to node N101. Also, the cascode amplifier 110 is biased by capacitor CBYPASS, connected between node N102 and the low voltage source. That is, capacitor CBYPASS generally filters out RF fluctuations and maintains a stable voltage at node N102 at the junction between resistors R102 and R104 to bias the gate of transistor 112. In addition, transistor 123 of the current mirror 120 biases transistors 111 and 112 of the cascode amplifier 110. A conventional cascode amplifier, such as cascode amplifier 110 of FIG. 1, typically has an output third order intercept point (OIP3) about 2-3 dBm better than a simple common source field-effect transistor (FET), for a given device size and bias.
However, the amplifier circuit 100 has a number of drawbacks. For example, transistor 112 limits the voltage swing that is available at the output node Nout, which limits the maximum linearity that can be achieved as input (or output) power is increased. The output power range over which optimum linearity is maintained is therefore reduced. The reduced range may be measured by the reduction in the output 1 dB compression point. Also, OIP3 values, which are sensitive to variations in temperature, fluctuate a relatively large amount.
For example, FIG. 2 includes graph 200, showing OIP3 values of cascode amplifier 110 over a range of frequencies (e.g., global positioning system (GPS) frequencies) at different operating temperatures (25° C., −30° C., 85° C.). Table 210 shows changes in bias current IBIAS and total current Itotal with respect to temperature. Itotal is the sum of IBIAS and IDD, although Itotal may be considered substantially the same as IDD since IBIAS is typically about five percent of IDD.
In particular, graph 200 shows an example in which IDD=5 mA and Vdd=+2.7V, resulting in a peak difference of 2.2 dB in OIP3, e.g., occurring at 1.600 GHz, when the temperature varies from −30° C. to 85° C. The changes in OIP3 are caused by resistance values of bias resistors (e.g., resistor R101) increasing at high temperatures, which reduces bias current IBIAS to the bias circuit 140. Also, transistor threshold voltages (e.g., of transistors 111 and 112) are reduced at high temperatures. As a result, total current Itotal is reduced and the OIP3 drops from the nominal 25° C. room temperature performance of the amplifier circuit 100. The situation is reversed when temperature decreases below the nominal temperature, in which bias current IBIAS and OIP3 increase.
Table 210 in FIG. 2 shows bias current IBIAS and total current Itotal corresponding to the different operating temperatures (25° C., −30° C., 85° C.). Referring to table 210, the change in total current Itotal from nominal 25° C. room temperature performance is about ten percent (e.g., from 5.0 mA at 25° C. to 4.5 mA at 85° C.) across the entire temperature range −30° C. to 85° C.